1. Field of the Invention
The present invention relates to a circuit for transmitting a control signal for driving a sense amplifier, and more particularly, to a circuit for controlling a sense amplifier which restores a signal that has been delayed by line loading for faster operation of the sense amplifier, where every one or every group of a few sense amplifiers is provided with one sense amplifier driver for faster data sensing of the sense amplifier.
2. Discussion of the Related Art
The sense amplifier detects, amplifies, and forwards as output a level of voltage or current of a received signal which meets a threshold value during a particular time region. The sense amplifier senses data stored in a memory and the like positively, and amplifies and forwards it as output. In general, the sense amplifier must be highly sensitive, fast, and operative in a wide voltage range, and must have a low power consumption and occupy a small area.
A background art sense amplifier will be explained with reference to the attached FIGS. 1-3.
FIG. 1 illustrates a block diagram of a memory, schematically. In FIG. 1, the background art memory is provided with an address generating unit 10 for generating an address and an address transition detecting signal ATD, a pre-decoder 20 for decoding the address generated in the address generating unit 10, a word/bit line decoder 30 for decoding a word line and a bit line in response to a decoded address signal generated in the predecoder 20, a memory cell 40 adapted to be accessed by a word line (WL) driven by the word/bit line decoder 30, a sense amplifier 50 for receiving data accessed in the memory cell 40 through bit line BL to amplify a weak signal, and an output latching unit 60 for latching a signal from the sense amplifier 50 in response to the address transition detecting signal ATD generated in the address generating unit 10.
The operation of the memory device having the aforementioned system will be explained up to the sense amplifier. The address generating unit 10 generates an address transition detecting signal ATD and provides a changed address when an address is changed. Address data from the address generating unit 10 is decoded in the predecoder 20, which enables a word line WL and a bit line BL relating to the decoded address through the word/bit line decoder 30, to select an intended memory cell 40. Then, data received through the enabled bit line BL is amplified in the sense amplifier 50. In this instance, a data sensing rate of the sense amplifier 50 is a major factor for determining an access rate for the memory.
FIG. 2 illustrates a background art circuit for controlling sense amplifiers in a memory. In FIG. 2, the background art circuit for controlling sense amplifiers in a memory is provided with a sense amplifier pull-up driver 51 and a sense amplifier pull-down driver 52 for driving sense amplifiers 50a.about.50n connected to one pair of bit lines BL and /BL representing positive and negative signals, respectively, and a sense amplifier driver precharge circuit 53 for precharging the sense amplifier drivers when the sense amplifiers are not in operation.
FIG. 3 illustrates waveforms of signals at different parts and peripheral important parts in FIG. 2. The operation between the sense amplifiers having the aforementioned system and the peripheral circuit will be explained with reference to FIG. 3. When an equalization signal EQ of the sense amplifier driver circuit is at low VSS, signals /SP and SN for controlling a sense amplifier driver are received, driving the sense amplifier drivers 51-52. Thus, sense amplifier drivers 51 and 52 generate /SNC and SPC to drive sense amplifiers 50a.about.50n. When the sense amplifiers 50a.about.50n are driven by /SNC and SPC of the sense amplifier drivers 51 and 52, the one pair of bit lines of BL and IBL representing a positive signal and a negative signal, respectively, are ready to transmit data.
In this instance, as shown in FIG. 2, when there are a plurality of sense amplifiers 50a.about.50n provided therein, if a transmission length of signals /SP and SN for controlling driving of the sense amplifiers 50a.about.50n is long, an accurate signal may not be delivered due to a signal loss caused by the transmission path, i.e., a line loading. Therefore, the background art circuit for controlling a sense amplifier may be susceptible to delays in the operation of the sense amplifier driven by a pull-up or a pull-down operation voltage caused by line loading, which causes major problems for users demanding fast and accurate operation, an ultimately degrades the product.